VHDL code of JK Flip Flop

library ieee;

use ieee.std_logic_1164.all;

entity jk is 

    port(

        j,k,clk:in std_logic;

        q,qn:out std_logic);

    end jk;

architecture behav of jk is 

    begin   

        process(j,k,clk)

        variable temp:std_logic;

        begin 

            if (clk='1' and rising_edge(clk)) then

                if(j='0' and k='0') then    

                    temp:=temp;

                elsif (j='0' and k='1') then

                    temp:='0';

                elsif (j='1' and k='0') then 

                    temp:='1';

                else    

                    temp:=not temp;

                end if;

            end if;

            q<=temp;

            qn<=not temp;

            end process;

        end behav;