VHDL code for Counter

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity count is 

    port(

        reset,clk:in std_logic;

        d_out:out std_logic_vector(2 downto 0));

    end count;

    

architecture behav of count is

    begin

        process(clk,reset)

        variable m:std_logic_vector(2 downto 0);

        begin 

            if(reset='1') then 

                m:="000";

            elsif (rising_edge(clk)) then 

                m:=m+1;

            end if ;

            d_out<=m;

            end process;

        end behav;