VHDL code for T Flip Flop

library ieee;

use ieee.std_logic_1164.all;

entity t is 

    port (

        t,clk:in std_logic;

        q,qn:out std_logic);

    end t;

    

architecture behav of t is 

    begin 

        process(t,clk)

        variable temp:std_logic;

        begin 

            if(clk='1' and rising_edge(clk)) then 

                if(t='0') then

                    temp:=temp;

                else 

                    temp:=not temp;

                end if;

            end if;

            q<=temp;

            qn<=not temp;

            end process;

        end behav;