VHDL code for 2:4 Decoder

library IEEE;
use IEEE.std_logic_1164.all;

entity decoder is
    port (
        i1,i2:in STD_logic;
        o1,o2,o3,o4:out STD_logic);
    end decoder;
   
architecture single_delay of decoder is
    begin
        o1<=((not i1) and (not i2)) after 5ns;
        o2<=((not i1) and i2) after 5ns;
        o3<=(i1 and (not i2)) after 5ns;
        o4<=(i1 and i2) after 5ns;
    end single_delay;