VHDL code for 2 bit binary adder

library IEEE;
use IEEE.std_logic_1164.all;

ENTITY gate2 IS
    PORT(
            i1,i2:IN BIT;
            o1:OUT BIT);
    END gate2;
   
ARCHITECTURE single_delay OF gate2 IS
    BEGIN
        o1<=(i1 AND i2) after 5ns;
    END single_delay;