VHDL code for COMPARATOR

library ieee;
use ieee.std_logic_1164.all;

entity comp is
    port(
        a,b:in bit;
        o1,o2,o3:out bit);
    end comp;
   
architecture single of comp is
    begin
        o1<=(a and (not b));
        o2<=(a xnor b);
        o3<=((not a) and b);
       
    end single;